A sample-and-hold circuit receives an electrical signal with one or more time varying attributes such as, for example, amplitude or phase and, in response to a sampling command event such as, for example, a clock edge, takes and holds a sample of the signal.
Sample and hold devices (hereinafter referenced generically as “S/H device(s)”), are used in a wide range of applications such as, for example, a pre-sampler within, or preceding a front end of an analog-to-digital converter (“ADC”), typically to present a value to the comparators of the ADC that is reasonably stationary for long enough to meet a set-up and hold time requirement of the ADC, or a “de-glitches” installed at the output of a digital-to-analog converter (“DAC”), typically to sample the DAC output at some time after the DAC clock and thus hold a steady-state analog signal level.
The sample that is held by the S/H device is, ideally, the instantaneous value of the signal that exists exactly at a given point in physical space at a given instant of time, e.g., the signal value at a sampling terminal of the S/H device at an infinitely precise time relative to an infinitely precise clock.
It has been long known, however, to persons of ordinary skill in the arts pertaining to S/H devices that actual operating S/H devices suffer from various non-ideal characteristics by which the actual sample at a given time after the sampling instant is not, in fact, the exact value of the input signal that was extant at that instant. These non-ideal characteristics include, for example, sampling jitter, meaning the statistical variance of the time difference between the ideal hold clock event and the instant that the S/H actually holds the sampled value; acquisition time, meaning the time required for the S/H device to charge the hold capacitor to the sampled signal value; as well as charge injection; clock feedthrough and pedestal error.
Various known methods are directed to reducing or compensating, at least in part, one or more of the above-identified non-ideal characteristics of actual S/H devices.
For example, the simplest signal switch component of an S/H device is a single transistor fabricated by a MOS process, such as a PMOS FET or NMOS FET. Each of the PMOS FET and NMOS FET is controlled by a clock signal that swings between the MOS supply voltage VDD and the system ground. An inherent problem faced by a single transistor PMOS FET or NMOS FET structure is that each requires a threshold gate-to-source voltage, generally termed VTH, to switch on, meaning to form a conducting channel extending under the gate from the source to the drain. The lowest signal voltage that can be transferred by a PMOS device is therefore equal to 0+VTH, and the highest voltage for an NMOS device is therefore equal to VDD−VTH.
To avoid this inherent shortcoming, and to provide other benefits known in the arts pertaining to S/H devices, the complementary MOSFET (CMOS) switch was introduced. CMOS switch S/H devices are well known in the S/H arts, as they were introduced decades ago. A typical CMOS switch includes a PMOS FET and an NMOS FET, connected parallel to one another with source-to-source and drain-to-drain connections. One ON-OFF S/H signal, typically termed a clock or CLK is connected to the PMOS FET gate and the complement of that CLK, which may be termed NCLK, is connected to the NMOS FET gate. The PMOS and NMOS FETs therefore turn ON and OFF concurrently, subject to time differences between the edges of the CLK and NCLK.
Related art CMOS switch S/H devices also have inherent shortcomings, though, including, as an illustrative example, a signal-dependent ON resistance of the CMOS switch, which in turn produces an inherent non-linearity.
Methods that have been, or are directed at this inherent non-linearity of CMOS switches have been long used and longer known. All have also been long known as having significant shortcomings. For example, one such method is to boost the gate control voltage “VG” to lower the “(VG−VS)/VS” variation caused by the signal variation at the source “VS” of the MOS switch. This method imposes costs, and has other non-ideal characteristics such as, for example, limited effectiveness and increased risks of accelerated device failure due to the higher the gate control signal level.
Another of these methods, often referenced as the “bootstrap” method, makes the gate voltage follow the analog input signal with an offset to turn the switch ON and to keep “VGS” constant, thereby maintaining a somewhat constant ON resistance. However, the offset voltage must be high enough to turn the switch ON with low on-resistance but, at the same time, must be low enough to limit the stress added on the gate to be lower than the breakdown level.
Another limitation of the bootstrap method, which has been long known in the arts pertaining to S/H devices, is that the bootstrap circuitry controls “VGS”, but provides nothing to control the source-to-body voltage dependence, or VSB dependence of the MOS devices on-resistance in the CMOS switch, which is another linearity error source. Conventional methods directed to reducing “VSB” related linearity error include forcing the error to zero by shorting the body terminals of MOS FETs to their source terminals while in the sample mode. These and other methods, though, have been long known as not attaining acceptable S/H device performance for many applications.